1. Technical Field
The present disclosure relates, in general, to a semiconductor memory device and, more particularly, to an erase voltage generation circuit generating an erase voltage being applied to the bulk of a memory cell and to a non-volatile semiconductor memory device having the same.
2. Discussion of Related Art
Generally, the erase operation of a non-volatile semiconductor memory device is executed by emitting the charges trapped in the floating gate to a bulk of a memory cell. In this case, an erase voltage is applied to the bulk of a selected memory cell. It is generally the case that the erase voltage generation circuit to generate the erase voltage is embedded in the non-volatile semiconductor memory device.
FIG. 1 shows a conventional erase voltage generation circuit. With a pumping operation, a high voltage generation unit 10 generates an erase voltage VERS that is applied to the bulk of the memory cells of a selected memory array MCARR, not shown in FIG. 1. A voltage level detection unit 20 detects the level of the erase voltage VERS to be provided to the memory array MCARR. Also, the voltage level detection unit 20 feeds back a level detect signal /XDET to the high voltage generation unit 10. The level detect signal /XDET is in the appropriate logic state according to the level of the erase voltage VERS.
To maintain the erase voltage VERS at the level equal to or more than a predetermined level, the pumping operation of the high voltage generation unit 10 is controlled by the fed back level detect signal /XDET. A control unit 40 generates an erase control signal XERSEN according to an external operation command CMERS and controls the high voltage generation unit 10 to be enabled. A discharge unit 50 discharges the erase voltage VERS at the level of power voltage VDD in response to the inactivation to logic “L” of the erase control signal XERSEN.
A level rising time is varied according to the number of memory cells being erased, that is, the number of memory blocks being erased, as illustrated in FIG. 2. In the following, the phrase ‘level rising time’ means the time required for the level of the erase voltage VERS being generated from a high voltage generation unit 10 to rise to a target voltage Vtag. In other words, the level rising time tA for small memory blocks in the voltage generation circuit results in an erase execution time being relatively short. While, the level rising time tB for large memory blocks is relatively long.
Therefore, an erase executing time is changed according to the number of the erased memory blocks in the conventional erase voltage generation circuit. In the following, the phrase ‘erase executing time’ means the time for executing erasing of a memory cell at which the erase voltage VERS is more than the target voltage Vtag.
However, in the conventional erase voltage generation circuit, there is the problem that it is difficult to set up an appropriate erase period. That is, if the erase period is set short, since the “erase executing time” is short, non-erased memory cells may exist in case that the number of memory block is large. If the erase period is set long, since the ‘erase executing time’ is long, over erased memory cells may exist in case that the number of memory blocks is small.